The invention relates to a clock signal generator for generating a clock signal with minimum phase jitter.
The generation of a clock signal by means of a DT oscillator (DTO: Discrete Timing Oscillator) is generally known.
FIG. 1 shows a DT oscillator according to the prior art, and said DT oscillator also forms part of the clock signal generator according to the invention. The DT oscillator is composed of an accumulator for adding a predefined digital incremental value which is present at a first signal input E of the accumulator to an accumulated digital value which is present at a second signal input of the accumulator and is buffered in a register of the DT oscillator. The register is connected to the output of the accumulator and is clocked with an input clock signal which has an input clock frequency fin. If the accumulator output value is higher than the value 2Kxe2x88x921 which can be represented on the basis of the predefined bit width K, the xe2x80x9coverflow valuexe2x80x9d 2K is simply omitted.
The DTO output signal if the DT oscillator which is output at the output A is illustrated in FIG. 2. The DT oscillator outputs a sawtooth output signal. Here, each sawtooth of the sawtooth output signal is composed of a plurality of steps with discrete amplitudes, the height of which corresponds to the incremental value applied and the width of which is determined by the clock period 1/fin of the applied input clock signal. When the overflow value is exceeded, the next step of the output signal A has a value which is reduced by this overflow value (modulo operation).
The sawtooth DTO output signal of the DT oscillator has a frequency fout in accordance with the following equation:
fout=fin*incremental/overflow valuexe2x80x83xe2x80x83(1) 
If the frequency of the input clock signal fin is very high in comparison with the frequency of the output clock signal fout, the most significant bit MSB of the DTO output signal can be used directly as a clock output signal. The direct use of the most significant bit MSB of the DT oscillator means that this method of implementation requires very little expenditure in terms of circuitry. However, the direct use of the most significant bit MSB of the digital output signal of the DT oscillator has the disadvantage that relatively high phase jitter occurs.
FIG. 3 shows the cause of the phase jitter which occurs at the signal output A of the DT oscillator illustrated in FIG. 1. The DTO output signal is represented by sampled values. The position of the sampling times migrates over the sawtooth output signal of the DT oscillator because the ratio of the output frequency fout to the clock frequency of the input signal fin is rational. The most significant bit MSB of the DT oscillator which is used as the output clock signal changes at a sampling time. The change in the most significant bit MSB of the DT oscillator, and thus the signal edges of the output clock signal, therefore deviate from the ideal phase relation. The ideal phase relation is given by that time at which the sawtooth output signal of the DT oscillator jumps from the overflow value to the value 0.
The case A illustrated in FIG. 3, with the sampled values a1, a2, constitutes one of the limiting cases, while the case B with the sampled values b1, b2 shows the other limiting case.
In the limiting case shown in case A, the sampled value a1 lies precisely at the value of the overflow value/incremental value. As a result of the incremental value being added to the sampled value a1, the sawtooth output signal reaches precisely the overflow value, with the result that the sawtooth output signal jumps back to the sampled value a2, that is to say to the digital value 0.
In the limiting case shown in case B, the sawtooth output signal has the sampled value b1 which corresponds precisely to the overflow value xe2x88x921. As a result of the incremental value being accumulated, an overflow occurs and the digital value b2 is output at the output of the DT oscillator.
As is apparent from FIG. 3, the maximum phase jitter is:
Jittermax=1/finxe2x80x83xe2x80x83(2) 
The higher the input clock frequency fin, the lower the phase displacement. However, the frequency of the input clock signal which is generated for example by a quartz oscillator and an analog pLL circuit can be increased only to a limited degree.
FIG. 4 shows an example of the phase displacements which occur with a conventional DT oscillator in which the ratio of the input frequency fin of the input clock signal with respect to the frequency of the output clock signal fout is 3.4. FIG. 4 shows a sawtooth profile of the DTO output signal and the signal profile of the associated most significant bit MSB of the DT oscillator.
The ideal phase relation is determined by the time at which an overflow occurs in the DT oscillator and the digital output signal jumps back to the value 0. The real phase relation of the DT oscillator is determined by the time at which the most significant bit MSB of the digital output signal has a falling signal edge.
The following applies to the chronological displacement between the real phase relation treal and the ideal phase relation tideal:
xcex94t=trealxe2x88x92tideal=Tin*DTOn0/incremental valuexe2x80x83xe2x80x83(3) 
Tin being the clock period of the input clock signal, that is to say:
Tin=1/finxe2x80x83xe2x80x83(4) 
and DTOn0 being the digital value of the DT oscillator after an overflow has occurred.
The DTO digital value after each overflow thus constitutes a measure of the time or phase displacement between the ideal signal phase of the DTO output signal and the signal phase of the most significant bit of the DTO output signal, it being possible to use the most significant bit MSB of the DTO output signal as a clock output signal.
For the chronological displacement after the DTO output value has the exceeded the value xc2xd*overflow, the following applies:
xcex94t=trealxe2x88x92tideal=Tin*(DTOnn0xe2x88x92xc2xd overflow value )/increment 
The object of the present invention is therefore to provide a clock signal generator for generating a clock signal with a minimum phase jitter, in which the clock signal acquired from the most significant signal bit of a DT oscillator has a minimum phase displacement with respect to the DTO output signal.
The invention provides a clock signal generator for generating a clock signal with minimum phase jitter at a clock signal generator output, the clock signal generator having:
a DT oscillator which is clocked with an input clock signal and which generates a periodic digital DTO output signal,
a phase displacement calculation unit for calculating the phase displacement between the signal phase of the DTO output signal and the signal phase of the most significant bit of the DTO output signal, and
a phase displacement reduction unit for reducing the phase displacement between the signal phase of the DTO output signal and the signal phase of the most significant bit of the DTO output signal as a function of the calculated phase displacement, the most significant bit being output with reduced signal displacement as a clock signal at the clock signal generator output.
The DT oscillator preferably has an accumulator for adding a digital incremental value which is present at a first signal input of the accumulator to a buffered accumulated digital value which is present at a second signal input of the accumulator.
The DT oscillator preferably has a register which is connected to a signal output of the accumulator in order to buffer the accumulated digital value.
The register of the DT oscillator is preferably clocked by the input clock signal with an input clock frequency fin in order to generate the digital DTO output signal.
The register of the DT oscillator is preferably reset if the accumulated digital value reaches a digital overflow value.
In one preferred embodiment of the clock signal generator according to the invention, the phase displacement calculation unit has a digital derivative unit which generates a clock pulse at each signal edge of the most significant bit of the DTO output signal.
The digital derivative unit of the phase displacement calculation unit preferably has here a plurality of gates and a register which is clocked by the input clock signal.
The phase displacement calculation unit preferably has a latch circuit for buffering the DTO output signal.
The latch circuit of the phase displacement calculation unit is preferably clocked here by the clock pulses which are generated by the digital derivative unit.
In one preferred embodiment of the clock signal generator according to the invention, the digital derivative unit preferably additionally generates a signal edge indicating signal which indicates, at each signal edge of the most significant bit of the DTO output signal, whether the signal edge is a rising or a falling signal edge.
The phase displacement calculation unit preferably has a logic circuit which subtracts, as a function of the signal edge indicating signal which is output by the digital derivative unit, half the overflow value or 0 from the DTO output signal buffered in the latch circuit, and divides the result of the subtraction by the incremental value in order to calculate a phase displacement signal which indicates the phase displacement between the signal phase of the DTO output signal and the signal phase of the most significant bit of the DTO output signal.
The phase displacement reduction unit of the clock signal generator according to the invention preferably delays the signal of the most significant bit MSB of the DTO output signal by means of a register chain, composed of a plurality of registers connected in series, in accordance with the signal delays occurring in the phase displacement calculation unit.
The registers of the register chain which are connected in series are preferably clocked by the input clock signal.
In one particularly preferred embodiment of the clock signal generator according to the invention, the signal, delayed by the register chain, of the most significant bit MSB of the DTO output signal is applied to a delay line, composed of a plurality of delay elements, of the phase displacement reduction unit.
In one particularly preferred embodiment, the phase displacement reduction unit has a multiplexer.
The multiplexer of the phase displacement reduction unit preferably has a plurality of multiplexer inputs which are each connected to a delay element output of a delay element of the delay line.
The multiplexer of the phase displacement reduction unit preferably has a multiplexer control input at which the phase displacement signal calculated by the phase displacement calculation unit is present.
The multiplexer preferably connects through a delay element output to the clock signal generator output as a function of the phase displacement signal which is present at the multiplexer control input.
In one particularly preferred embodiment, the delay elements of the delay line are delay elements of analog design.
In one alternative embodiment, the delay elements of the delay line are delay elements which are of digital design and which are clocked with the input clock signal.
In a further embodiment of the clock signal generator according to the invention, the signal, delayed by the register chain, of the most significant bit MSB of the DTO output signal is applied in parallel with the control of a plurality of latch circuits, each of whose inputs is connected to a signal phase of a multiphase clock, and each of whose outputs is connected to a signal input of the multiplexer.
Preferred embodiments of the clock signal generator according to the invention are described below with reference to the appended drawings in order to explain features which are essential to the invention.